Wednesday, September 26, 2007

Parting thoughts on

A few random observations today coming back to the Valley from the conference in Austin:

The group is ramping up an effort to set common standards for debug across Power chips and tools. IBM exec Chris Ng who heads the effort is reaching out to industry for feedback. Right now his group is discussing adopting the Aurora interconnect from Xilinx.

IBM's Hollis Blanchard is starting a separate effort in to define virtualization for Power, especially in the embedded world. Among its needs are virtual I/O support in chip sets, the kind of thing the PCI SIG is developing for x86 computing.

To make this all run right we will need not only new hooks in the processors and memory management units but in the embedded OSes, too. So far the RTOS crowd is keeping mum on any plans to support virtualization, Blanchard reports.

The group has at least half a dozen other initiatives in the works, many of them led by resourceful IBM middle managers. Whether the efforts will drive the Power community forward remains to be seen, but there is clearly no lack of effort.

Finally, a quick welcome back to Tracy Richardson. The former chief executive of StarGen is now heading up marketing at interconnect specialist Tundra Semi. Tundra is cooking up a concept it calls intelligent I/O, but it's still in stealth mode, he told me at the event.

Tuesday, September 25, 2007

Power's bus woes

I thought Intel had on-chip bus troubles because it chose to get stuck in the arcane world of PCI bus semantics. That's a happy old jalopy compared to the accident waiting to happen over at Power city.

The four chip makers of the Power world—AMCC, Freescale, IBM and PA Semi—all preach the silicon religion of the day. We're headed for a future of heterogenous multi-core chips. They'd like to ride a common on-chip bus to get there, but I don't see how it's going to happen.

Freescale created its CoreNet on-chip bus as part of the multi-core architecture it debuted in June that will take it from a family of 45nm many core parts next year into a 32-core future someday. For now, Freescale is keeping a lid on the specs of the bus, not even sharing them with Power partner IBM Corp.

IBM, which carries a lot of the water for the Power group, had been plowing the way for on-chip buses with its PLB-4 aka Core Connect. Just when or whether IBM pushes that to a PLB-6 is still unclear. Meanwhile, AMCC which lacks the resources of its two bigger partners has licensed the ARM AXI bus, and startup PA Semi uses its own proprietary on-chip bus.

The group which supposedly oversees the Power architecture—all decisions are made by a separate committee of IBM and Freescale engineers—says it is investigating a 10-50 Gbyte/second high-end on-chip bus. Don't hold your breath. For today, everyone in this group is going their own separate way into the multi-core future, an approach this already fragmented architecture can hardly afford.

Sunday, September 23, 2007

A look inside the x86

As usual, last week's Intel Developer Forum was a fire hose of information with several useful droplets here and there buried in a huge flow of generally useless hype and executives who were both amazingly available to the press and well trained about not saying anything substantive to them. The big interconnect bits included the news about USB 3.0, wireless USB 1.1 and PCI Express 3.0 I have blogged about below.

There were two other interconnect tidbits somewhat buried in my EE Times wrap up in print this week. Intel gave a marketing name to what it had been calling CSI. However, the company gave almost no detail about the QuickPath coherent interconnect to be used starting with its Nehalem processors late next year, except that it will gluelessly support two and four-way servers. Analysts think it will be more than just Intel does HyperTransport, four years late. But other than the unauthorized but well detailed white paper from fellow journalist David Kanter, little is publicly known.

Separately, it was interesting to hear from Ajay Bhatt that Intel uses PCI software semantics in its proprietary on-chip interconnects. This is probably one of several Achilles Heels that will make it hard for the world's largest software company to step graceful and late into the world of system-on-chip design. This ain't the stepwise world of the 986 running at 6 GHz anymore. Good luck!

Wednesday, September 19, 2007

On USB 3.0 and PCIe 3.0

On Day 2 at IDF in San Francisco, I discovered an interesting little detail of the proposed USB 3.0. A chart (right) displayed on the exhibit floor showed the cabling has not only the two separate lines specified by USB 3.0 but another line dedicated to any USB 2.0 traffic.

I guess that means the cables are three times as expensive as today's cables, I told the engineering manager from Foxconn manning the booth. He assured me there is work afoot to keep costs down despite this and the fact there is an extra set of mechanical links in the connector as well. He also said the spec is pretty far along at this point, something the diagrams made clear.

Separately, I listened to a chalk talk by Ajay Bhatt, chief I/O architect and Intel fellow, who filled in some missing details about Intel's Geneseo proposal. Turns out this was actually Intel's proposal for PCI Express 3.0 as made to the PCI SIG. Intel could not reveal that fact last year because the proposals were under NDA, so it released the details as a proposal for an industry interconnect to accelerators. Hmmmmm.

Turns out Intel really likes PCI software semantics as a unifying and simplifying element. It even uses them as a way to describe internal USB and other silicon blocks inside its chip sets and processors linked over its proprietary on-chip interconnects.

How quick is QuickPath?

Thanks to David Kanter for unearthing and sharing more details on Intel's next processor bus than the chip company is ready to disclose. Basically Intel was only willing to share the name—QuickPath—the fact that it connects up to four processors and will debut in Nehalem chips next fall.

Kanter concludes from an analysis of Intel's patents QuickPath will be a 20-bit wide bus and run at 4.8-6.4 GHz, faster than what AMD has planned for HyperTransport in that same timeframe. As Kanter sees it, AMD is going to have a hard time competing with Intel starting next fall when Nehalem debuts through to when AMD gets all its server CPUs revved up on HyperTransport 3.0 by the fall of 2009.

But let's not kick them while they are down, Kanter said. So I note that Tarari chief architect Eric Lemoine said he thinks HyperTransport is a superior architecture to Geneseo because it sports lower latency and provides good access to cache lines. OK, I said something nice for the poor underdog of the PC industry.

Attack of the giant USB

Pat Gelsinger says an amazing 6.2 billion USB devices have shipped to date, more than 2 billion of them just last year. So when Intel says it will ratchet USB 3.0 up to 4.8 GHz, give it new flow control mechanisms and make it support copper and optical—you gotta say look out Firewire. The Intel folk even tested their nearly 0.75 spec at 25 Gbits/s in a software simulation and aim for a protocol that could hit 100G someday.

The reality check, as NEC told me, is that USB 3.0 may need to cut in half its five meter reach to hit its goals and silicon and software will require a major upgrade. Meanwhile, Intel is trying to push wireless USB to 1 Gbit/s before there is hardly any certified WiMeda products for the 480 Mbit/s products, that really only get to about 40 Mbits/s.

That's Intel for you. Lots of ambition and as much execution as it can muster from such a broad industry.

Monday, September 17, 2007

Dispatches from IDF: USB 3.0 debuts

Why, oh why did I wait until the night before to troll through the sessions for this week's Intel Developer Forum. Oi Vay! So now I find out Intel is ready to talk turkey about USB 3.0 on Tuesday.

Last year one of my key PCI Express contacts said there was a lot of work happening in the background on USB 3.0, making use of the 5 GTransfers/second the Express 2.0 spec now enables. Had I only checked back a few weeks ago I might have had a scoop! Now I'll have to elbow my way to the news with the rest of the IDF crowd.

The IDF Web site just talks about a fast synch-and-go interconnect and promises a technical overview and timeline for the technology to come to market. Sounds like it is pretty well thought through at this point. Will we see Gbit/s wired links in 2009? Stay tuned…or post a scoop ASAP as a comment if you know about this stuff.

Also on tap at IDF this week: More details about Geneseo, a collect of interconnect technologies enabling co-processing over Express and the Intel front-side bus. This is Intel's answer to HyperTransport and AMD's Torenza program.

In addition, IDF is host to several discussions of 10Gbit Ethernet and data center interconnects including something under the marketing banner of Intel's Virtualization Technologies for Directed I/O. Whadeva that means!

I hope I get to find out more about all this in between a half dozen sessions touting Intel's upcoming 45nm Penryn processors which Intel hopes will grab all the headlines tomorrow, leaving AMD's latest quad and three-core 65nm CPUs in the dust.

Party time for PCIe

This week's Intel Developer Forum may act as something of a coming out part for PCI Express 2.0. PLX and Mellanox are both touting new Express Gen2 products today and I expect to see news from others when I troll the IDF floor this week. Pericom fired the started gun with a pre-announcement of their chips a few weeks ago, but now multiple companies have real, tested and shipping silicon.

Intel has already announced one chip set for Express 2.0, and I expect to hear about more members of the family this week. AMD and NVidia will likely follow suit to talk about their chip sets expected to emerge in systems before the end of the year.

Computer graphics and muscular PC servers are plowing the way on this change. Admittedly the data path and backplane silicon on routers, switches and other high end comms and military gear hit 6.25 Gbits/second and beyond a while back and they are gearing up for 10G now. But this week's news is the great bulk of the volume computing world is driving these fast interfaces into mainstream electronics.

True, the biggest signal integrity design challenges don't really start to kick in until you get a bit north of the max 5 GTransfers/second Express 2.0 enables. But the PC crowd sees that next step forward and has started real lab work on the migration into that zone too with Express 3.0.

Gentlemen and women, start your engines.

Friday, September 14, 2007

Hot little WiMax handsets?

That's the implication I got from a teaser for a Sept. 26 Motorola press conference at WiMax World in Chicago. The news blast is titled: 'WiMax: Broadband in the palm of your hand,' and includes presentations from Moto, Sprint and Rogers execs.

My read on this sector is it is still way too early for WiMax silicon that fits into the power consumption envelope of a handheld. My gut tells me we are at least 2-3 years away from that day. Perhaps this is just a tease for a pretty boring review of what's happening in WiMax, I don't know.

Once again, I reach out to you, dear readers. If you know what Moto is up to here or have any other news tips coming down from WiMax World, let me know. I will be in Austin that week and will miss the event so I'd like to hear anything you pick up as a comment here or an email to

Thursday, September 13, 2007

Medical's wireless squeeze

You don't find many requirements tighter than these. Power consumption at 100 nanoW and duty cycles of operation just 0.01 percent of the time. That's the goal for wireless links in cardiac implants that aim to stay active 7-10 years before a surgical replacement is needed.

Thanks to Paul Stadnik, RF engineering manager at implant maker Biotronik, for passing on to me a milestone standards makers hit this summer for this technology. The TG30 group responsible for medical standards under the European Telecommunications Standards Institute ratified in July a new low power, low duty cycle protocol for the Medical Implant Communications Services band blessing this use in the 402-405 MHz MICS band.

The standard is used to let implants communicate status information typical once a day with a home monitoring system. The FCC is studying a similar standard. To date it only recognizes this use in the 401 and 406 MHz MICS sidebands, but a ruling aligning US rules with those in Europe could come any day.

Biotronik fielded some of the first implants to use MICS based on its own ASICs. But a handful of chip makers are delivering MICS chips now including AMI Semi, Texas Instruments and Zarlink.

Meanwhile TG30 has started a two-year effort to identify new spectrum needs for implants that need more than the 100 Kbits/s or so you can get with MICS and fancy modulation schemes. Brain implants that capture signals and transmit them wirelessly to controllers for artificial limbs are one of the chief applications for a broadband implant standard.

Wednesday, September 12, 2007

Home health gadgets ride USB, BT

Tomorrow's consumer health care gadgets will ride Bluetooth and USB—at least an early wave coming next year. That's because the Continua Health Alliance officially backed those interconnects as part of their first-generation logo requirements announced today. Continua is an ad hoc standards group that includes a who's who of medical device companies trying to enable home health care systems.

Its no surprise the ubiquitous USB will be big in these future gadgets. It's more of a big deal that Bluetooth got the nod because it is not as broadly used yet, outside cellphones. Though it is mature, there are more emerging wireless options than you can shake a stick at. As I blogged earlier, researchers are prototyping medical devices with cellular, RFID, ultrawideband and Zigbee nets.

Add one more to the heap. Texas Instruments announced today its SimpliciTI network protocol, a proprietary low-power radio frequency (RF) protocol targeting simple, small RF networks of less than 100 nodes. TI baked support for the protocol into its MSP430 microcontrollers and CC110x/CC2500 transceivers. TI says it aims to complement Zigbee, reaching into smaller nets than Zigbee would typically embrace.

Tuesday, September 11, 2007

I/O goes virtual

Serag GadelRab, author of the IEEE Micro article on 10Gbit Ethernet that I bogged about last week, was right about one thing. Virtualization is becoming an increasingly important part of the differentiation in both processors and I/O chips.

AMD rolled out this week the Rapid Virtualization Indexing feature built into its Barcelona chip. It boosts virtualization performance as much as 25 percent when apps support it, AMD claims. Intel is right on top of this trend too.

I learned from Intel yesterday its I/O Acceleration Technology (IOAT) effort is now coming under the umbrella of a larger group of technology initiatives called Virtualization Technology Connectivity (VTC, to keep the acronyms going). Although Intel rolled out a few new features as part of IOAT this year so far, it sounds like a lot of the juice in the future is coming from its work supporting virtualization in hardware.

Specifically, at the Intel Developer Forum the company will be talking about Virtual Machine Device Queues. These VMDQs (to stir the alphabet soup) will reportedly help boost throughput on virtual traffic from 4 to 10 Gbits/s, providing they are supported by software vendors. VMWare is on board this particular advance from Intel which it simply calls Net Queues.

The VMWares of the world are no doubt getting stretched every which way as the major processor and Ethernet companies try to get them to support special hardware hooks they are baking into their parts. This is to say nothing of the PCI I/O virtualization work which is nearing completion and already getting put into silicon.

And coming soon to a server near you, 10GBase-T products from Intel. Stay tuned!

Monday, September 10, 2007

ATCA can survive Intel's departure

Intel Corp. sold off its single-board computer business to Radisys Corp., according to a report today in EE Times. In his blog, my colleague Loring Wirbel asks what impact this may have for the overall ATCA movement Intel helped spearhead and for Intel's credibility generally.

My sense is ATCA will do OK. As reported earlier it has taken much longer than most people thought for this market to come to fruition, a fact many attribute to the slow-moving nature of the comms business. You can also blame the resistance of OEMs to shift to a standard chassis. But this ship is launched and no doubt Intel will continue to provide some level of support to a movement which promises a broad homogenous market for its chips.

As for Intel's credibility, I understand the x86 giant has gone hot and cold on many initiatives in its past. But this move is one of the last shoes to fall in Intel's long restructuring to refocus on its computer business and back off from the many loss-making ventures in comms it launched back in the days before the dot-com bust when the company wanted to be in everything from network processors to data center outsourcing.

The fact is Intel has regained significant territory against its key competitor Advanced Micro Devices. Its 65nm Caneland chip is not far behind AMD's much vaunted Barcelona released today. And next week we will get an earful about Intel's first 45nm Penryn CPUs, leapfrogging AMD.

In the end, the ATCA community has less to fear from this news than the folks at AMD.

Friday, September 07, 2007

...and one more thing

About that iPhone price cut.

The iPhone is a huge success in terms of a good base product. I have seen everyone from casual friends to Andy Bechtolsheim toting the handsets and praising them for being the Web done right on a cellphone. No more seven clicks to get to a strange carrier network with useless test blurbs on tiny displays. This is a couple quick hand motions to the real Web. Brilliant.

The device has also become a cultural icon. It represents the shift of the geeky computer and the Web into fashionable, useful consumer communications devices. Everybody gets that.

But Apple realized for all its achievements, the iPhone was not on track to being the kind of financial success it needed to avoid becoming a drop in the billion-unit cellphone ocean. There was no big missing feature. In a world where consumers have a choice of several really great free phones, the iPhone just cost too damned much.

Apple was on track to sell maybe two million iPhones in its first year, according to published reports. Not bad for a computer company starting from zero in the phone business, but not enough to establish Apple as the next Nokia, which is Steve Jobs' goal.

The $399 price—and the $100 rebates—are steps in the right direction. But my belief is the iPhone is not 400 times better than the great Samsung, Motorola and Nokia phones offered for free. The pressure is on to see if Apple can innovate, get volume and make money in this mature and competitive market. Expect more price cuts.

Why Wi-Fi iPod?

OK, I know iTunes has sold a bazillion songs and TV shows and movies. But as Steve Jobs pointed out in his open letter on digital rights management not long ago, the vast majority of songs on the average iPod are ripped from CDs or free peer-to-peer sites.

I still recall giving an iPod-loving teenager an iTunes gift card as a birthday present a couple years back. She glared at it like it was an ugly alien. "What is this for?" she asked.

So I doubt there will be a huge rush of teens flowing into Starbucks to use their new iPod Touch devices to buy music on iTunes. Too bad Apple didn't consider Bluetooth for ad hoc links to let people share songs between their iPods. This was a feature users really want and one the otherwise bedeviled Zune got right.

The iPod Touch won't flop. There are always Apple fanatics eager to show they have the latest expensive status box and will pay the ~$300 just to have the multi-touch display and the cool-looking album cover flipping interface. Wi-Fi will probably be something they learn to turn off because it sucks the battery dry too fast. Ah, consumer electronics!

Thursday, September 06, 2007

Rx for medical messaging

I am still unpacking my notes from a trip to the annual Engineering in Biology and Medicine Conference, this year in Lyon. An email from Leonardo Estevez of Texas Instruments whom I met there jogged my memory about one effort.

At the conference I saw plenty of papers about medical consumer devices using Bluetooth, ultrawideband, Zigbee, cellular and RFID. Indeed, there's an embarrassment of riches these days and a growing problem in interoperability for the devices people imagine will soon appear on future home and personal area nets.

The IEEE 11073–20601 group, also known as the personal health data group, is working on a standard application layer mapping that would link standards for existing 11073 medical data formats to the wealth of wireless transports. Rather than write separate mappings for each wireless transport, they want to write template each can use. But the group needs broader representation to do its work. They are woefully underrepresented in Zigbee for instance. If you want to be part of this effort contact

Separately, Leonardo of TI tells me he sees an opportunity for a kind of medical SMS service that alerts family members and doctors with simple, standardized and machine-readable notes.

"If for example, I receive a message that tells me my grandmother hasn’t talked to anyone on the phone for the last two days or has been forgetting to take her drugs – I might want to call her. Physicians are also interested in this kind of information," Leonardo writes.

Sounds like a good idea. Leonardo is trying to find a forum, the 20601 effort or perhaps a new group, to champion it.

Monday, September 03, 2007

A benchmark for 10G Ethernet

Thanks for bearing with my disappearance into the French Riviera for a week. I am back from diving into the deep blue Mediterranean Sea and ready to dive into the deep goo of interconnects.

Thanks to Serag GadelRab for supplying a copy of his very detailed and thorough technical review of techniques used in 10G Ethernet network interface cards in the May-June edition of IEEE Micro. It is indeed a deep dive into the issues. If you haven't read it yet, go find it.

Serag calls for a benchmark to gauge the effectiveness of various stateless and TCP offload approaches across different systems and apps. He does a good job making the case for that need by describing the incredible complexity and diversity of past and future techniques for handling the problem of matching these fast networks to relatively slow servers. Serag's article reinforces my own feeling of being somewhat in the dark about what will be the winning approaches here. So I second his call for a benchmark.

I'd like to hear from readers on this score. Do we need a benchmark for measuring the various 10G Ethernet approaches, and if so what would it be and who should create it?
As usual, you can post a comment here or email me at

Incidentally, Serag concludes that stateless NICs working with multicore processors will take the mainstream in 10G Ethernet. TOE chips with RDMA will hold a niche in high performance computing and storage, putting competitive pressure on Infiniband in its current home court. That's not the view I got from HP recently.

If Serag is right, that explains why Mellanox has embraced a hybrid Infiniband/Ethernet strategy, and why despite its current business success, validated by its recent successful IPO, Mellanox has not attracted any direct competition in Infiniband silicon.

Serag makes two other insightful observation about next-gen 10GE chips in his article. They will need to support two new features to handle the rise of traffic from multiple guest sessions in virtualized software environments. Vendors will try to eke out unique competitive approaches in how they support multiple logical data paths, he said. Secondly, these chips will have to learn how to handle switching on the NIC inside the server.