Sunday, April 29, 2007

Ethernet takes on Infiniband

Startup Net Effect officially makes a second go at the market for enhanced Ethernet adapters starting today with the release of its NE020 card. The company claims the dual-port 10Gbit/second Ethernet card closely approaches the throughput, latency and cost of Infiniband, currently the performance leader in data center networking.

It's worth noting that none of the enhanced Ethernet cards based on the iWarp standard have had much market traction yet, despite the fact some of the heavy hitting Ethernet vendors have been behind this effort for several years. There are plenty of reasons for that. The initial Gbit cards were too slow, costly and didn't have mature software support.

Net Effect said it spent most of last year ironing the bugs out of its initial single-port 10G products and now it expects to see volume sales for the dual-port cards starting this fall. We shall see.

As always, things keep moving. The problem for the iWarp crew these days is that Intel and Sun have developed their own approaches, driving TCP offload back to their multi-core CPUs. That solves the main problems iWarp was designed to solve several years ago—getting the full throughput of 10G without overloading the CPU. Thus these new CPUs could severely limit the available market for iWarp adapters.

Net Effect claims the new concern today is getting lowest possible latency and consolidating around few data center interconnects. I don't know if that's really what data center managers are thinking or not, but I am open to hearing from anyone who knows.

The other big problem for Net Effect is that this new product comes out at a time when virtualization is really hot, but the PCI SIG standard for handling I/O virtualization over Express is not quite done. The startup will spin a new ASIC next year for use on the motherboard that it expects will comply with the then-completed standard. But if the NE020 does not take off, Net Effect could run out of money before it gets to that opportunity.

Friday, April 27, 2007

Sun spins its wireless chip link

I wasn't able to attend the open house at Sun Labs Thursday, but I did see the event included mention of a new twist on the group's research on its Proximity interconnect. Proximity is a capacitive coupling technique originally intended for use linking processors inside a supercomputer. The project seems to have gone through a makeover since Sun lost its bid to build for DARPA a prototype system using Proximity.

At yesterday's event Sun discussed Project Sedna, a multi-terabit data center interconnect based on Proximity. The R&D project is aimed at “future data center interconnects that scale to thousands of compute nodes and to bandwidths of tens of terabits-per-second,” according to description on the Sun Labs Web site. It suggests Sun researchers are extending the chip-to-chip Proximity links into a broader systems switch fabric. The technology “will drive the convergence of today's network and storage architectures towards a single networking infrastructure,” Sun claims.

In the past, Sun has said getting proper alignment of the capacitive coupling links was one of its chief challenges. It will be interesting to see whether it can solve this problem and extend the technique into use beyond a CPU cluster, possibly surpassing the work chip makers such as IBM are doing with chip-level 3-D interconnects. If anyone had a chance to burrow into the details of Project Sedna at the event, please post us an update here.

Thursday, April 26, 2007

Log in and say “Ahhh”

A growing class of medical devices are moving into the digital, networked era, and they need standards to make sure they interoperate. Enter the IEEE 11073 personal health data work group.

The committee, that now includes nearly 100 people from more than 50 organizations, started its work last July. So far, it has defined use cases, drafted a broad set of requirements, and created a draft for a common data exchange protocol.

The group aims to define nine standards in its first round of work. Beyond the data protocol, they include a common data format specification and specs specific to six device types--a blood pressure monitor, a pulse oximeter, a heart/pulse rate meter, a scale, a thermometer and a glucose meter. The group will also write a technical report that describes the use cases and environment for networking such systems.

Thanks to Doug Bogia, chairman of the committee and a member of Intel's digital health group, for providing an update on the committee's work. The Intel group helped found the Continua Health Alliance that is trying to pave the way for such systems. We baby boomers will likely link many of these future devices to our PCs and cellphones someday.

Wednesday, April 25, 2007

A new day for interconnect designers

You can learn a lot from reading the classified ads. I picked up one on the Signal Integrity email list recently that gave an interesting reality check about high-speed interconnect design in communications. An ad for a senior engineer for the Internet Systems division at Cisco Systems had the following eyebrow raiser:

“We are now engaged in the design of 6-8Gbps serial link interfaces. The Senior SI Engineer is expected to model legacy systems for 6-8Gbps operation, anddesign new systems to work at even higher line rates.” To handle that work the candidate needs to be able to “generate guidelines for new [chip] packages...and design experiments to” evaluate and characterize high-speed serdes. Besides having experience with a wide variety of high-speed design tools and test gear the person needs “a solid grasp” of a range of techniques including “microwave theory.”

The ad posting validated something I heard a while back from Todd Westerhoff, a senior SI engineer at Cisco who left last year to join the EDA world. Engineers in top tier comms companies are headed into a whole new era of design at 6G bits/s+. They have to become deeply astute about the details of things like chip packages as well as highly nuanced second-order signaling effects at the chip and board levels. That will require new tools, tests, gear and techniques unlike anything they have seen before.

Grab a coffee, sharpen your pencil and welcome to the new era in comms design.

BTW, I am still looking for any pointers about why Google is hiring signal integrity engineers for its Google Platforms group. I'd love to get my hot little hands on the specs of a Google server or systems interconnect!

Tuesday, April 24, 2007

A new wireless wire in the home


Eric Broockman of Alereon has posted an interesting item on his UWB blog about the future of UWB over coax. He suggests that the technology holds real hope for broadband home networks at 390 Mbits/s today and 1.6 Gbits/s in the not-too-distant future--far beyond the 100 Mbits/s+ MoCA spec. All it needs is a standard, some development of the software stack and adoption by gateway and set-top vendors.

That's a pretty big mountain to climb, given that MSOs are leery of anything that smacks of wireless or less than full nailed down content protection. What's more, it's not clear what the forum would be for setting this standard and there is a ton of software development work required to make it work.

I'd love to see a Gbit/s home net, but the real problem with home nets today is not so much that we lack bandwidth. It's more that there is a lack of focus among the many options offered today, as I noted in a CES roundup on the topic.

Monday, April 23, 2007

High performance pointers

HPCwire has a good profile of Woven Systems Inc. and its new high performance 10G Ethernet switch that aims to supplant Infiniband in the data center. The company claims its EFX 1000 will deliver 10G (half what Infiniband can do now) at four microseconds latency (twice or more than IB) while consuming 16W per port.

Woven put dynamic congestion management features into its ASIC. That's a hot new feature, but given that an IEEE effort is still in the works in the area, it is only likely to appeal to users who crave the performance and can't wait for the standard.

Not surprising then, the company's first beta tester will be a national lab benchmarking its system against Infiniband. Woven hopes to get four beta users up and running to shake out the system before it is in production this fall.

Separately, Engadget has a much more spartan, but still interesting write up on the first FPGAs to plug directly into a Xeon processor front-side bus. Xilinx and Altera demonstrated their wares at last week's IDF Bejing. It marks a small start on the road to standard co-processors using the PCI Express Geneseo extensions and, ultimately, Intel's Common System Interconnect which I expect to hear more about this summer.

Sunday, April 22, 2007

May the force be with you

Magnetic and capacitive coupling techniques for wireless communications have been gaining traction in medical devices. The latest example comes from the William Demant group that showed hearing aids using magnetic coupling to link to each other or to a bridge device that uses Bluetooth to connect the hearing aids to cellphone and MP3 players. (My EE Times story on the topic should appear here sometime Monday.)

There's still a fair amount of secret sauce in these approaches also used by med electronics giants like Medtronic. I have yet to hear of anyone today pushing for a standard or merchant silicon in this sector.

For a time startup Aura Communications tried to bring this technology directly to consumer systems, but they have fallen off the radar screen. Ditto the Proximity interconnect Sun Microsystems was developing for chip-to-chip links for a prototype supercomputer until it lost federal funding. Perhaps it's time to look at this approach again.

Thursday, April 19, 2007

Modeling format percolates


Proponents of a new approach to high speed signal integrity modeling are turning up the heat on their efforts.

I reported from DesignCon in January on Cadence Design Systems' work on a new way to securely interrogate high speed chips. Now former Cadence signal integrity guru turned consultant Donald Telian suggests vendors may be getting ready to rally around the approach, much as they responded to his call 15 years ago to form the IBIS (I/O Buffer Information Specification) group.

"We may be on the verge of a new modeling format," writes Telian in a contributed article recently submitted for publication in EE Times.

The gist of Telian's point is that Cadence's algorithmic modeling approach "can compile Tx/Rx signal processing structures and algorithms in their native formats into executable models for an SI simulator…The beauty of the Cadence solution is that, in theory, the same models can be used by both the SI simulators and the test & measurement equipment."

The issue at hand is getting chip makers, EDA and test companies to understand and accept this new approach. No specific news on that front, but with Telian's enthusiasm on the topic, I suspect plenty of people are hearing about it.

Wednesday, April 18, 2007

Wireless USB slowly steps forward

The PC-centric version of ultrawideband took a small step forward this week, when three companies became the first to have their wireless USB (WUSB) silicon certified by the USB Implementers Forum.

Intel and NEC have host chips ready to go and Alereon and NEC have chips for peripherals. The spec can deliver wireless links with data rates up to 480 Mbit/second over three meters.


The group said full products should ship by June, at least nine months later than originally scheduled. The group finished its spec in May 2005. At the time it hoped to have chips certified by the end of 2005 and products shipping in the fall of 2006.

It's not clear whether the group has lost momentum since that time when as many as 40 companies said they were interested in building some form of WUSB chips and the group believed it would knock down all the global regulatory hurdles still in front of ultrawideband technology.

Cost and integration challenges are still ahead. To really make this market rock engineers need to get standalone chips down to $5 and even integrate WUSB into existing chip sets for systems such as digital cameras, notebook computers and media players. These issues just take time as proponents of Bluetooth, just now coming into its stride, have learned.

Tuesday, April 17, 2007

Here comes CSI

No, not Crime Scene Investigation. Common System Interface, the replacement for the traditional front-side bus on an x86 processor. Intel confirmed publicly for the first time it is rolling out this long rumored beast when its quad-core version of Itanium code named Tukwilla hits in 2008.

Intel hopes to leapfrog the HyperTransport interconnect archrival Advanced Micro Devices has been using on its Opteron and Athlon chips with something that could scale to linking as many as 128 CPUs in a non-uniform distributed system.

It may take until this summer before the company starts the dribbleware process of disclosing bit-by-bit technical details about CSI. Some decisions about just what CSI is have not even been made inside Intel yet, said Jim Fister a technology strategist in Intel's Digital Enterprise Group in an interview after a keynote at the Gelato Ice conference today.

As I have said before, interconnects such as CSI are among the key technology planks of the multi-core computing world, so watch this space.

Swimming upstream, Part 2


As usual with press releases, yesterday's announcement from Dolphin had less substance than it promised. The company has only ported some software from startup StarGen it acquired in January to its existing Scalable Coherent Interconnect (SCI) adapter card. The new code enables a more Socket-like environment for supporting TCP, UDP, IP and other standard protocols and provides some optimization for Oracle RAC and MySQL Cluster applications.

The interesting bit is that Dolphin will rev its ASIC for a new card to ship later this year. The new chip will integrate both SCI and PCI Express, probably the 5 Gbit/s version, on a single die. Dolphin says that with the new ASIC, sustained card data rates should jump from 8 Gbit/s to more than 10 Gbits/s and application latencies should fall below 2.26 microseconds.

Dolphin knows it is swimming against the tide of momentum from Infiniband already shipping 20 Gbit/s products, albeit with higher latencies. Thus it is focusing on the still-emerging market for database clusters and it is leveraging the PCI Express juggernaut.

What this means to me is the Dolphin folk may not make any big market splashes anytime soon, but they are smart folk with plenty of good technical detail on their Web site and worth keeping an eye on.

Monday, April 16, 2007

Swimming upstream?

I just got a news blast from Dolphin about their new clustering interconnect, leveraging technology from their acquisition of StarGen. I'm trying to get an interview to get a better read on the details of what the technology is and where they are taking it. I assume they are aiming it at business clusters because they know Infiniband, Myrinet and Quadrics have the technical computing space locked up. Stay tuned.

Tessera in IBM's shadow

Tessera formally launches its MicroPILR approach to stacked packaging today, based on the technology it acquired back in May 2005 from Japan's North Corp. Little did the company know its announcement would get upstaged by news from IBM last week about Big Blue's advance in the more forward-looking through-silicon via die interconnect.

Whatever the marketing climate, observers are taking a skeptical look at MicroPILR, which uses tiny columns to pack more links between two stacked chips. Neither the economics of this approach nor the extent of buy in from key substrate makers is clear, observers say. What's more other package-on-package technologies are already ramping into high gear with the backing of Jedec standards and known tool flows. This could be a tough sell for Tessera.

Sunday, April 15, 2007

PMC pushes SAS pedal to the metal


PMC-Sierra appears to be first out the gate with serial-attached SCSI silicon running at the 6 Gbit/second data rate of the SAS 2.0 spec. But its not clear what real value the company will get for pushing the pedal down on its Tachyon controllers purchased from Agilent a year ago, besides brief bragging rights. Four or five other controllers are expected out in the fall, at least for testing at the SAS 2.0 plugfest sponsored by the SCSI Trade Association.

STA expects the full "eco-system" of SAS 2.0 products--including drives, cards and controllers-—won't be widely available until next year, setting up the first 6G-enabled systems for early 2009. In the meantime, PMC hopes its chips can help consolidate electronics and bolster some management features in 3G SAS arrays and server blades.

STA president Harry Mason said the SAS 2.0 spec will not enable new kinds of systems so much as help expand the capabilities of existing servers and storage systems. As the author of the interconnect blog, I loved his response to my question about the impact of 6G.

"More and more it seems like systems availability is tied to the performance of the interconnects," he said. Amen!

Friday, April 13, 2007

The road to 3-D chips

I learned a lot about the future of chip-to-chip interconnects from covering IBM's announcement yesterday that it is ready to build its first commercial chip using through-silicon vias, holes drilled directly through two die and filled with a metal link. My colleague Mark Lapedus had plowed significant ground on the topic in a story from the February ISSCC conference.


Perhaps the biggest news nugget I turned up pursuing this story yesterday is that the International Technology Roadmap for Semiconductors will sport a first-ever section on the roadmap for through-hole vias when it is published late this year. Thanks to Sitaram Arkalgud, who runs the interconnect group at Sematech, for giving me the run down.

There's plenty happening here, it is interesting technology and has huge implications for the future of chip and system design, a topic I will burrow into more in a story in Monday's EE Times.

So now that I have come up to speed a tad on the topic, look for me to weave this thread into the fabric of my interconnect coverage from time to time. I welcome your inputs on the topic by making a posting here or emailing me at rbmerrit@cmp.com

Thursday, April 12, 2007

Monstrous days for UWB?

The proponents of ultrawideband technology are at an interesting crossroads. The engineers are scrambling to make the underlying technology work while the business execs are trying to prove to the market it is real.

Yesterday's news from Tzero Technologies is a case in point. The company said it is working with cabling giant Monster to develop products that will hit the retail shelf this fall to wirelessly link DVD players, set-top boxes and digital video recorders.

I happen to know the engineers just down the street from me in Sunnyvale have been working overtime for quite awhile to get the technology to a state where it does what its being advertised to do—make consumer and media friendly connections at hundreds of Mbits/second. UWB has held both great promise and huge technical challenges for years. Some of the early pioneers such as Time Domain and the Freescale UWB group are no longer around.

Now the business execs over at Tzero, one of the best of breed UWB startups, are really cranking up the heat with this very public promise to make a big splash in a short amount of time. Cross your fingers, and bookmark the Tzero blog.

Let's hope they tame the wireless beast for the sake of this technology which has long promised to be a huge enabler and the engineers sweating out the nuts and bolts details to make it happen. The digital home has enough problems without inviting in a Frankenstein.

Wednesday, April 11, 2007

More shoes to drop for TOEs

Storage networking pioneer Larry Boucher is wiggling his TOEs today. Larry makes the point that--in the midst of all the recent hubbub about Fibre Channel over Ethernet and planned enhancements to Ethernet--a good TCP offload engine still offers the best bet for data center storage.

Alacritech, Larry's startup that invented TOE, claims its four-port Gbit Ethernet cards deliver 100,000 IOPS, as much as some 4 Gbit Fibre Channel cards. He says the proof will be in the pudding as reviewers begin comparison tests of Alacritech cards under Microsoft's TCP Chimney and competing Fibre Channel options.

We shall see. Alacritech rolled out today some updated cards and software. But it remains to be seen how the TOE issue will shake out between Alacritech's partial offload style, the RDMA Consortium's full offload approach which has the backing of a broader group of OEMs and chip makers and the emerging multi-core approaches such as Intel's IOAT and Sun's Neptune that claim to eliminate the need for TOEs altogether.

Excuse the bad pun, but there are a lot of shoes left to drop on this issue.

Tuesday, April 10, 2007

MoCA maker adds whipped cream


I give Entropic Communications credit for expanding its base beyond the Multimedia over Coax home net standard with its planned purchase announced this week of RF Magic Inc., a designer of digital TV tuners. My colleague Loring Wirbel gives the recipe behind this combination over at EE Times.

Home nets will be a smorgasbord of everything from MoCA and HomePlug and HPNA to Wi-Fi and sneaker net. So no one will have a huge market and everyone will need to find ways to broaden their product portfolios. Kudos to Entropic as one of the few startups in this area to recognize that business reality early on.

Monday, April 09, 2007

RIO perks in the base station

Let me get my head out of the data center for just a minute to say thanks to Tom Cox, executive director of the RapidIO Trade Association, for forwarding a very interesting document on a proposed base station for next-generation cellular systems. The document details a test bed from Ericsson for Long Term Evolution, the next big step in the cellular infrastructure.

LTE will provide download speeds as fast as 100 Mbits/second, according to proponents. That’s two to four times as fast as the high-end cellular systems being discussed today. Tom sends me this document because the system is dripping with references to use of serial Rapid IO as a key interconnect for applications data. One rack mount system proposes use of 12 four-lane sRIO links as a fabric switch in a core ATCA system that houses more than 100 DSPs. The system also makes heavy use of Gbit Ethernet.

Dan Bouvier, a system architect at AMCC who helped develop RIO in his days as a Motorola PowerPC guru, forwarded the same Ericsson document to me as unusual in its level of technical detail. RIO is replacing a proprietary ATM-based fabric used in Ericsson base stations today, Bouvier noted.

Ericsson, long a backer of RIO for DSP farms, demonstrated the system at the 3GSM World Congress in Barcelona in mid-February. It was based on FPGAs that will be converted to ASICs by 2008 when the system is expected to ship, according to a report from my colleague John Walko that provided some good perspective on LTE and WiMax.

Saturday, April 07, 2007

Weaving a new fabric

My editors posted my latest story on Fibre Channel over enhanced Ethernet (FCoE) faster that I thought! The story gives a little more color on the Cisco patent mentioned below as well as some deeper details about the outlook for FCoE silicon.

Basically, if all goes well chips could hit as early as 2009 and systems perhaps 18 months later. The chips are likely to require an addition state machine to process congestion management algorithms as well as 3-5x deeper buffers to handle virtual channels, depending on the details of the final protocol. The chips are expected to be used widely in adapter cards, switches and gateways.

I had the chance late Friday to talk with Claudio DeSanti, vice-chair of the T11 committee and technical leader of Cisco's data center business unit. He made a couple interesting points.

Perhaps the most interesting was that the T11 work on FCoE will be based on existing traffic-pausing techniques in Ethernet. Ethernet enhancements being worked on in IEEE 802.1au and being discussed beyond that will be great, but not necessary.

"If we were forced to wait before we do our thing it could delay us a couple years, so what we are doing (in T11) has to be agnostic of any Ethernet extensions. If you have those extensions, things get even better," he said.

This is a practical approach, but I sense most products will be based on something closer to the whole enchilada including congestion management and priority-based pausing to make this work well. That will require vendors closely track work in T11, 802.1au, some efforts in the Internet Engineering Task Force and maybe other groups still to be decided. The priority pause work, for instance, doesn't have a defined forum yet.

That's an ambitious web to weave, but once that is in place, you can do a version of Ethernet that does not drop packets and has significantly better latency. Most observers expect the resulting technology will nibble at the low end of Infiniband in clusters and dampen enthusiasm for iSCSI at the high end of storage. But as we all know nothing ever goes away.

"We have and will continue to build iSCSI products. In no way do we see this as the end of iSCSI," said Anthony Faustini, a product line manager in the Cisco group. He might have said the same about Infiniband.

As my EE Times story says, the next big milestones will come in June with presentations on FCoE at the T11 meeting in Minneapolis and July when 802.11au hopes to select one of four proposals for Ethernet congestion management. Until then, stay tuned!

Friday, April 06, 2007

A bestseller for networking


Here's a piece of interesting weekend reading for all you interconnect mavens out there: US patent application number 20,060,098,681.

This is Cisco's patent request for Fibre Channel over Ethernet and as Linley Group analyst Bob Wheeler points out it’s a broad one, pointing to many of the Ethernet enhancements under discussion in the industry. Although Cisco was one of many companies publicly supporting the concept in an announcement made just this week, the patent dates back to May 11, 2006. It's authors, Luca Cafiero and Silvano Gai, left the Italian brain trust in Ethernet at Cisco to join startup Nuovo Systems that has its sites set on FCoE.

No doubt patent applications have been and will be flying from many other companies as work gears up to define a next-generation Ethernet for the data center. Everyone wants a piece of this pie.

I'll digest what I have learned about the effort this week for a Monday posting. Until then, happy reading. If you have any observations on the Cisco patent or the FCoE effort in general, post them here or drop me a line at rbmerrit@cmp.com

Thursday, April 05, 2007

More people pile on FC-over-E

The formal announcement about Fibre Channel over enhanced Ethernet hit this morning. It has no substantial technical detail in it. However it does add a few names to the list of supporters beyond what I have previously reported.


As of today it is public information that Brocade, EMC, Emulex Corp., IBM, Cisco spin-off Nuova Systems, QLogic, and Sun Microsystems are part of this party. What the press release doesn't say, but you will find in EE Times and here on Monday is the timing and silicon impact of this move as well as some news about a very interesting pending patent that apparently covers the technology. Stay tuned.

Wednesday, April 04, 2007

Free advice for speeders

Consultant Eric Bogatin has posted his latest five talks on signal integrity and there's more to come. There's a nice mix of high level talks (e.g. "The Signal Integrity Survival Guide") and nuts and bolts detail (e.g. "Designing a Transparent Via"). You have to go through a free registration to get the PowerPoint.

This guy is prolific with more than 100 articles and columns already on his site from classes he gives here, there and everywhere. Valley mavens note Eric's next class in San Jose is April 19-20, and there's a "Where's Eric" box to find out when he comes to your town.

Tuesday, April 03, 2007

The great Ethernet debates

Sun and Chelsio went toe to no-toe today with competing announcements about their Ethernet plans with and without TCP Offload Engines. Sun tapped Marvell as a partner for its version of 10G Ethernet leveraging its multithreaded processors while Chelsio became the first iWarp card maker to say it is using the Open Fabric software for Linux.

How the battle over TOEs will play out is still far from clear. Expect Alacritech who got the whole TOE conversation started to chime in again soon.

Analyst Bob Wheeler of The Linley Group says either way Ethernet will be the winner in the data center. But the rest of the iWarp crowd also needs to get its software act together and demonstrate broad interoperability with lots of products.

Maturity for iWarp "is taking longer than expected and that's opening a door for Infiniband," Wheeler told me today.

Monday, April 02, 2007

Last call for a Hoti

April 9 is the deadline to submit a paper for the Hot Interconnects conference. The annual confab at Stanford University is a back-to-school must for I/O mavens in fields ranging from on-chip processor-memory interconnects to wide-area networks. Organizers say "Contributions should focus on real experimental systems, prototypes, or leading-edge products and their performance evaluation." Amen.

So, get those papers in ASAP, and don't forget to call me a couple weeks before the show to tip your news!

Data center nets circa 2009


I have sunk my teeth into this CEE concept for enhanced Ethernet and I am not letting go. This week I want to dig into what the data center networks will look like in 2009. That means I need to get more clarity on CEE, Infiniband, Fibre Channel, iSCSI and any other contenders to paint a picture of where we are headed.

Everybody wants to be the converged network for networking, clustering and storage. What's the reality? If you have any insights you want to share, post them here or drop me a line at rbmerrit@cmp.com.


The concept may be all the more interesting because CEE hits at the same time as integrated AMD Fusion and Intel Nehalem processors that might include key underpinnings for I/O.

 
interconnects