Wednesday, December 05, 2007

Inside the x86

A week or so ago I asked readers if they had any skinny on Intel's thinking about SoC interconnects. I didn't hear anything back, but the reality is I have a fair amount of background on the subject…and I learned some interesting new wrinkles doing a report to appear at EE Times on Monday.

What I already knew: Intel has announced its Quick Path Interconnect as a upgrade for its front-side bus to appear in Nehalem CPUs starting in 2008. It is only for the hardy few co-processor types who need a fully coherent link. The Geneseo technology it is developing as a candidate for PCI Express 3.0 is the link for everybody else.

What I have learned: In addition to these external on-chip interconnects, there is one or more internal Intel interconnects the company plans to support.

What's more I also talked to Chuck Moore of AMD about their use of coherent and non-coherent HyperTransport links as their main SoC boulevards. Intel and AMD have clearly been courting third parties to hop on their different buses. Chuck said these two pairs of links are probably all anyone will ever see in the emerging world of x86 interconnects.

But "an interesting question is how these two pairs of standards will start to mingle," he said, suggesting multi-protocol links serving multiple purposes.

In addition, "there could be interesting protocol extensions beyond coherency for the next generation of HyperTransport," Moore added. Rather than communicating and synchronizing through memory, devices could link up in ways that "are more optimal," Moore said.

Just remember, dear readers, for this strategic peek into the future of X86 SoCs I charge you all of zero dollars. So, next time I ask for a tip, please drop a line or post a note to keep this little economy flowing, mon freres.

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