Wednesday, November 14, 2007

Gearing up silicon networks

Kudos to IEEE Micro for a solid issue on the topic of on-chip networks. The best article for my money is the report on the December 2006 Stanford workshop on this topic.

According to the report, the gathering identified a laundry list of technical challenges. Chip networks require at least ten times too much power and have far too high a latency. For example, they scoped out a theoretical chip design in the year 2015 using 256 cores and concluded it would use 20 percent of its 150W budget just on linking the cores.

What I thought was most useful here was the research agenda the group scoped out based on its analysis. They called for new encapsulation methods and libraries in design tools because the circuits and architectures used for silicon network are not compatible with today's CAD flows. Designers also will need formal verification methods and queuing analysis tools to replace simulation which will become inadequate.

They also said we need work on new low voltage signaling technologies, 3D stacking to reduce the length of on-chip wires, on-chip photonics that can be 15-20 times faster than today's wiring and tools that more accurately model traffic on these silicon systems. It's an ambitious agenda, but without these advances engineers won't be able to create tomorrow's multicore processors.

1 comment:

Assaf said...

To read more about on-chip photonics as a mean of dramatically reducing on-chip networks' power consumption:

http://www.cs.columbia.edu/~luca/research/pnocs_HOTI07.pdf

http://www.cs.columbia.edu/~luca/research/pnocs_DAC07.pdf

 
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