Monday, November 26, 2007

Battling bottleneck breakers

Rambus and IBM are squaring off on whether it's better to bust through the memory bottleneck with new signaling or packaging technologies. Both approaches look like contenders in the 2010 timeframe.

Our EE Times report today talks about Rambus' plans for demonstrating at its Tokyo developer conference this week a 32x clock multipler of 500 MHz memory channels. The channels enable 16 Gbits/s transfers and ultimately terabyte/second throughput between a microprocessor and its main memory.

IBM has shown proof points for 3D stacks that could enable a great gob of SRAM to sit on top of a multi-core microprocessor linked by fast direct-metal connections. Analysts said that could hit the market in 2010-class Power CPUs.

Other shoes are yet to fall. Sematech said this spring it planned to detail a market roadmap for 3D stacks before the end of the year. Jedec defines the standards for memory interconnects, so it has a major voice here. The good news is there is a diversity of good work on this nagging problem.

1 comment:

Anonymous said...

Many design problems boils down to optimizing power efficiency. This is often the case even with the memory sub-system. - And especially so with mobile battery powered devices.

The memory bus power can be optimized by minimizing both bus capacitance and signal swing. Short bus helps in both. Therefore face-to-face bonding of memory and logic is considered optimal. (3DIC / Trough-silicon-vias add more stray capacitances.)

Serial links won't come for free : Serdes logic needs to be very high speed. This fits poorly with the requirement of low power. Also the silicon area needed won't come for free. Furthermore high speed needs higher signal swing in order to maintain sufficient signal-to-noise marging (i.e. open enough eye).

Serial links fit for the limitations of circuit boards - But cannot replace optimized F2F/3DICs..

 
interconnects