Tuesday, September 25, 2007

Power's bus woes

I thought Intel had on-chip bus troubles because it chose to get stuck in the arcane world of PCI bus semantics. That's a happy old jalopy compared to the accident waiting to happen over at Power city.

The four chip makers of the Power world—AMCC, Freescale, IBM and PA Semi—all preach the silicon religion of the day. We're headed for a future of heterogenous multi-core chips. They'd like to ride a common on-chip bus to get there, but I don't see how it's going to happen.

Freescale created its CoreNet on-chip bus as part of the multi-core architecture it debuted in June that will take it from a family of 45nm many core parts next year into a 32-core future someday. For now, Freescale is keeping a lid on the specs of the bus, not even sharing them with Power partner IBM Corp.

IBM, which carries a lot of the water for the Power group, had been plowing the way for on-chip buses with its PLB-4 aka Core Connect. Just when or whether IBM pushes that to a PLB-6 is still unclear. Meanwhile, AMCC which lacks the resources of its two bigger partners has licensed the ARM AXI bus, and startup PA Semi uses its own proprietary on-chip bus.

The Power.org group which supposedly oversees the Power architecture—all decisions are made by a separate committee of IBM and Freescale engineers—says it is investigating a 10-50 Gbyte/second high-end on-chip bus. Don't hold your breath. For today, everyone in this group is going their own separate way into the multi-core future, an approach this already fragmented architecture can hardly afford.

1 comment:

Anonymous said...

Since Freescale has DSP's and PPC Processors with RapidIO, and IBM has ASIC Cores, and the New AMCC PPC460GT integrates a high-performance Power Architecture CPU core with Serial RapidIO, would it not make sense to take this interconnect to the inside of the chips. RapidIO is independent of PHY layer and has GSM (Global Shared Memory) for multi-core. Time for Power.org to consider RapidIO?

 
interconnects