Wednesday, September 19, 2007

On USB 3.0 and PCIe 3.0

On Day 2 at IDF in San Francisco, I discovered an interesting little detail of the proposed USB 3.0. A chart (right) displayed on the exhibit floor showed the cabling has not only the two separate lines specified by USB 3.0 but another line dedicated to any USB 2.0 traffic.

I guess that means the cables are three times as expensive as today's cables, I told the engineering manager from Foxconn manning the booth. He assured me there is work afoot to keep costs down despite this and the fact there is an extra set of mechanical links in the connector as well. He also said the spec is pretty far along at this point, something the diagrams made clear.

Separately, I listened to a chalk talk by Ajay Bhatt, chief I/O architect and Intel fellow, who filled in some missing details about Intel's Geneseo proposal. Turns out this was actually Intel's proposal for PCI Express 3.0 as made to the PCI SIG. Intel could not reveal that fact last year because the proposals were under NDA, so it released the details as a proposal for an industry interconnect to accelerators. Hmmmmm.

Turns out Intel really likes PCI software semantics as a unifying and simplifying element. It even uses them as a way to describe internal USB and other silicon blocks inside its chip sets and processors linked over its proprietary on-chip interconnects.


Anonymous said...

I had a different impression from this year's WinHEC where multiple companies spoke about the future of PCIe 3.0 including AMD, Microsoft, Intel, and a number of device vendors. In one panel where all of the vendors were present they stated that the four functional proposals called Geneseo were not the only proposals put forth to extend PCIe. AMD had made multiple proposals including what would become the announced Gen3 signaling and scrambling proposal. They also stated that with the exception of the gen3 signaling, the extensions would be released as ECN to PCIe 2.0 and then rolled into 3.0.

Seems to me that when you break down what is called Geneseo, the proposed functionality isn't that significant nor is it accelerator specific. Given this is all in the PCI SIG, any proposal is going to under go change such that the end specification only bears marginal resemblence to the original proposal.

Geneseo is more marketing that substance when you listen to what Intel has stated for the past year. Intel's real value is in their QuickAssist software not a minor set of enhancements to PCIe (and given the world demands I/O software be open source, it is not clear how they will maintain any real value here). I think most people would take issue with Intel claiming PCIe 3.0 is basically what they proposed when multiple vendors have already stated at WinHEC that there will be much more than the Intel and IBM proposed (can't forget IBM who was in the press when this came out in response to Torrenza but now seems to have fallen off the radar).

Anonymous said...

Intel is out marketing AMD and people are surprised? Intel is making a mountain out of a mole hill and people are surprised? Geneseo was a rushed out anti-Torenza marketing campaign and nothing more. Intel has to keep beating the drum on Geneseo because they made such a big deal out of it when they knew it to be far from monumental. Their real power and the real story is in the licensing of the FSB and the coming QuickPath and it was clear listening to the various talks at IDF that they are already looking to position Geneseo as just enhancements PCI Express. Surely this is the marketing machine looking for a soft landing once people see how little there is to these proposals.

The Intel proposals, correction, the Intel and IBM proposals - can't forget their prior partner in this endeavor - were at best, modest functional enhancements to PCIe. Both companies touted them as specific to accelerators when anyone who comprehends even a sliver of how PCI works knows they apply to any IO device and slice across all market segments.

Look at them in a bit more detail. First one is data reuse hints. All that means is the IO device sets a bit or two in the PCI transaction to help the chipset be a bit smarter about how processing is accomplished. Hardly a revolutionary idea to set a bit in a transaction to act as a hint on what to do upstream. It is true that it will take some intelligence to know when to set the bit but listening to Intel talk, it is clear that the rules for setting it will be defined by the chipset providers who will likely publish a white paper to make everyone do it one way. Intel is smart enough to know anytime they get fancy, it fails so expect it to be nearly idiot proof and simple. The mole hill gets to be prairie dog size.

Next proposal is to provide more relaxed ordering. Intel's talk largely focused on ordering within a chipset but at least one speaker indicated it applies to switches as well. No rocket science here since PCIe ordering rules are what they are - highly restrictive so they want let out their waist bands to enable transactions to be processed a little less serially. Sounds more like just specifying a new ordering rule set and may be set another bit in a transaction to know that the new rules apply and it is done. This seems like one of those been there, done that functions since other IO have offered such capability. The prairie dog hill is now moving towards an Appalachian foot hill.

Next proposal is atomics and how they will change the way IO is processed. Intel repeatedly stated at IDF they want the same programming models as on processors. If you check out Intel CEO's speech, he talked about Larrabee and how it will have the same programming model as x86. Can we add 2 + 2 and get both the Nvidia killer device as well an accelerator to take on Cuda and AMD's Fusion or ATI's graphics? Atomics are hardly new so adding them to PCIe isn't that difficult in either hardware or software so yet another minor bit of functionality and the mountain grows a bit taller. The story shifts West and the mole hill is now the size of the Rockies.

Next proposal is active power management. AMD set the bar on power management and with the world going green, everything is about power management. Ottellini's speech made it clear that Intel is all about power management and best performance per watt. So what does it really mean for PCIe? Don't need to be a Mensa kid that power management is just defining a set of power states and the controls to transition into or out of a given state. Seems like this already done with mobile products today to save battery power. Cannot fathom why Intel keeps saying this is just about accelerators. Oh wait, forgot, they are fighting Torenza with Geneseo so in marketing, anything goes even if it, well, just marketing. The hill is not the size of Mt. Hood and growing taller.

It was a surprise to see that their lead guy state that PCIe gen3 is part of Geneseo and that Intel thought of it all. My memory must be fuzzy since I could have sworn that gen3 as stated by the PCISIG for years now as providing 2x bandwidth. Who would have not thought that 2x bandwidth and cutting 20% of the encoding overhead also leads to lower latency? Guess I'm not surprised that Intel takes credit for an AMD proposal if what you say is true but that is what marketing is about - co-opting good ideas and making them your own while positioning the guys who thought of it all are falling further behind. Intel has good marketing. They know how to manipulate the press. Get used to it. The mole hill dwarfs K2 but remains on a dangerous precipice waiting for people to forget this was a non story.