Wednesday, August 08, 2007

It's 8 GT/s for Express 3.0

Not surprising the PC industry should place cost and compatibility over raw performance. That was the result of a six-month debate on the maximum throughput target for PCI Express 3.0 announced today.

A few years ago, the PCI SIG debated whether Express 2.0 would double the theoretical 2.5 GHz rate of its initial version or go for the gusto and try to match up with the world of 6.5 GHz serdes and interfaces set by the telecom world. Yep, they opted for 5 GT/s. The PC has always been about good enough performance and massive volumes based on keeping a tight lid on costs, so today's decision on 8 over 10 GT/s for the third gen of the interconnect is not a huge surprise.

Perhaps more interesting will be details of Express 3.0's new encoding scheme which will break with 8b/10b encoding and what kind of equalization it will employ. The group did not specifically say 3.0 will be fully backward compatible with both today's 5 and 2.5 GHz products, but I think that level of compatibility was a key factor in deciding on 8 GT/s.

3 comments:

Anonymous said...

I think it will be interesting to see how PCI-SIG can acheive 8GT/s sans 8b/10b encoding. I think they might employ adaptive equalization.

So Express is way ahead of it's peers Hyper Transport and RIO. RIO and HT has to do a lot to catch up with Express. I won't be surprised in the coming years Express will make a severe dent in the market of RIO and HT unless both RIO and HT ramp up to their level.

saturnengr said...

This creates an interesting consequence which follow logically from the decision to go with 8Gbps. 10Gbps standards will suffer.

Historically, the 8Gbps vs 10Gbps decision revolved around the receiver equalizers and hence signal integrity. Going to 8Gbps means not having to support non-linear DFE equalizers, i.e. supporting cheaper, easier linear analog equalizers. Because of the area, power, and other issues with non-linear DFE equalizers, PLLs, and other high speed circuits, an 8Gbps PHY should be smaller and lower power than a 10Gbps PHY.

However, from PCI Express comes other standards. Most PHY designers target a number of other standards designed around a basic PCI Express PHY: SATA, XAUI, KX4, SRIO, GE, Fibre Channel, etc. The incremental design cost for these additional standards is justified by PCI Express volumes paying for the majority of the design costs. Unfortunately, a 8Gbps PHY using a linear equalizer would imply 10Gbps standards cannot be supported. Most 10Gbps standards require a non-linear DFE-type equalizers, so not supporting DFE equalizers means standards such as CEI-6LR, 10Gbase-KR, XFI, CEI-12SR/LR and others no longer have the volume of PCI Express to offset the development costs.

My fear is that not supporting 10Gbps actually will harm the the 10G market place. Not having the volumes of PCI Express will delay development of many 10G standards. Given that we're seeing 3-4 years between PCI Express standards, we're probably looking at a delay of 3-4 years for these 10G standards which require DFE equalizers, unless some IP company can justify a new development effort to make a DFE-base PHY. Note that it is not competitive to use a single PHY with selectable DFE and non-DFE based IOs. And building a DFE-based PHY for PCIe if all other IP vendors are building non-DFE-based PHYs, the DFE-based PHY is at a serious disadvantage in terms of area and power consumption.

Although many will argue that 10G standards have high volumes or will have high volumes, compared to PCI Express, nothing on the market even comes close.

Anonymous said...

Please read the announcement once again.

PCIe gen1 2.5 GT/s was 2 GT for data and .5 GT/s for 8b/10b encoding.

PCIe gen2 5.0 GT/s was 4 GT for data and 1 GT/s for 8b/10b encoding.

PCIe gen3 is 8 GT/s for data and does not use 8b/10b.

Each step function provides 2x performance of the prior version.

PCIe 3.0 will require full interoperability with the lower signaling rates. Yes, this means supporting 8b/10b for the prior versions and then switching to the new scheme for 8GT/s for data.

The logic behind the decision was a combination of sensitivity to power consumption as well as the ability to re-use a large portion of the existing industry ecosystem. The result remains 2x the performance while paying close attention to the realities of power and cost in any high volume market space.

As for other interconnects, if they care about power, cost, etc. then they will follow a similar course for the 2010 time frame that PCIe 3.0 is targeted. I don't see any reason why HT, RIO, or should Intel decide, even CSI would not follow the same course as they all are operating under approximately the same constraints. As for other IO technologies such as SAS/SATA, Ethernet, IB, etc. all of these technologies have different operating constraints as well as economic tolerances. Fortunately Ethernet and IB have already defined their 10 Gbps offerings (albeit Ethernet has multiple flavors with different encodings to deliver a 10 Gbps data while IB has a 10 GT/s with 8GT/s data). The only high volume IO that might be impacted is SAS/SATA and for that, the roadmaps show a 2x signaling ramp to 12 GT/s with 10 GT/s data. Some PHY vendors produce offerings for this standard as well so they may have some amount of challenges but given the power constraints are different, they may not face so arduous a problem as some might contend.

 
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