Thursday, July 05, 2007

Driving Gen2 Express

Moving to the PCI Express 2.0 is no slam dunk. The new spec requires more attention to managing jitter, simulating channels and signal integrity among other things. Kimkinyona Fox, a PCI Express product marketing manager at Rambus which sells Express intellectual property and design support, walked me through some of the challenges.

Engineers working with Gen2 Express need to track multiple kinds of jitter—random and deterministic—to finer tolerances than with the 1.0 interconnect. The magic number here is getting to less than 50 picoseconds of jitter in 100,000 data samples.

Gen 2 supports common, data or separate transmit and receiver clocks. The latter approach can be useful when running Express over a noisy wire. However separate clocks are so hard to manage the official Gen2 spec doesn't even try to define how to go about it and says interoperability is not guaranteed. "I found that amusing," said Fox

With tight tolerances all around, engineers need to simulate channel effects much more carefully with Gen2 than the existing Express spec so they can set effective but not restrictive guard band limits. In addition, Gen2 supports signal de-emphasis at 6dB in addition to the existing 3.5 dB support.

Despite the problems, Intel already has demoed a working Gen2 workstation chip set and third party graphics chip. Those chips and other graphics and server chips using Gen2 are expected to ship this year. They will be followed by ASICs in the works for high-end data center storage and networking systems likely to ship in 2008-9. And someday, probably a few years out, high-end peripherals such as high-def video decoders will start to transition to Gen2 which promises to deliver about 80 percent of its 5 Gbit/s theoretical transfer rate.

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