Friday, June 15, 2007

Nudging HyperTransport

In an effort to keep its Itanium processor in the news, Intel engaged in the all-too-common practice of a little spec strip tease yesterday, disclosing three or four new factoids about the road map of the server CPU. The big deal to me was a little more detail about its plan to replace its CPU front-side bus with a HyperTransport competitor called the Common Systems Interface.

Intel is still not giving details about CSI yet, not even its name. But yesterday it publicly said it will use the interconnect on both a 2008-class Itanium 2 chip called Tukwilla, and at least one Xeon and common south bridge I/O chip in the same time frame. Execs also said the link will have unique reliability and scalability features, probably alluding to the support both for SMP and NUMA systems an Intel server technologist told me about earlier this year.

I'm hoping for a briefing with Intel before the summer is out to fully take the wraps off CSI and see how it compares with HyperTransport defined by archrival AMD. The other big question is whether Intel will license the interconnect to third parties, a move that would make a lot of sense to me but create some real costs and management issues for Intel.

If anyone else has more G2 on this situation, feel free to post what you know here or drop me a line at rbmerrit@cmp.com.

1 comment:

Anonymous said...

Let's see:

(a) Hypertransport is backed by the open, industry standards Hypertransport Consortium.

(a') CSI is Intel proprietary.

(b) HTC defines the HTX connector to enable I/O devices to attach to a platform.

(b') Intel states I/O should only be through FSB or PCI Express.

(c) HTC only defines non-coherent HT specifications. AMD retains sole control of coherent HT.

(c') CSI is coherent and Intel retains sole control of CSI.

(d) HT link technology uses similar physical layer techniques as PCI Express. HT generally operates at higher signaling levels that PCI Express.

(d') CSI is publicly unknown. However, Intel has touted serial for years so one would expect a similar approach as HT.

(e) HT has a number of advanced protocol features and demonstrated strong performance.

(e') Intel has never been shy about using what works and leveraing ideas from all over to create their technology. They claim they do it better since they learn from their and other's mistakes but unclear if that is always true.

(f) Physical layer convergence or uinversal physical layers is coming close to reality. There will not be one specification but the techniques and priniciples are very close no matter that protocol lives above.

(f') Aside from protocol, how different will HT, CSI, and PCI Express be at the end of the day? Will anyone care sans the low-level hardware designers?

(g) AMD defines Torrenza to provide high-speed I/O and accelerator attach via HT and PCI Express.

(g') Intel defines Geneseo to provide high-speed I/O and accelerator attach via PCI Express and FSB. Likely it will have CSI since FSB will fade away over time.

In the end, Intel is playing catch up with HT. It was only a matter of time. The question is whether Intel will do something better and reserve it only for their use or will they open up and accept that open, industry standards are to everyone's advantage. What has been proven time and again is the cost of proprietary technology is more than just the hardware. It is the wasted expenditures of dealing with all of the differences which far exceeds the benefits Intel often puts forward. AMD and Intel need to reconcile this arena because in the end, customers are making it clear that processors don't matter, OS don't matter, only solutions they actually see and use matter. Those that hide the hardware completely demonstrate that the focus of these two companies on one upmanship is misspent and harms all.

 
interconnects