Tuesday, May 22, 2007

Tuesday's goulash

The main news of the day, as far as I can tell with my eyes still bleary, is that Broadcom has rolled out a chip for 10G backplane Ethernet. (Wish they would have briefed me!) Some forward-looking engineers think silicon based on this KR spec will someday find its way into multicore CPUs, too.

On a completely unrelated note, I was down at the PCI SIG conference yesterday for a detailed briefing. I guess it just goes to show how hard it is to get an entire industry to develop and move to faster interconnects when the briefing for 2007 sounds pretty much like the briefing for 2006. Talk about leftovers!

Al Yanes, the IBM chip set engineering manager who heads the SIG these days, gave some details about the multiple levels on which work is slogging forward on PCI Express 3.0. It's still up for debate whether this will be an 8 or 10G spec and whether it could still sport compatibility with today's version 1.1. "If this were easy, we'd be briefing you on the details today," Yanes said.

Bumped into the father of Express, Ajay Bhatt, at the Dev Con. He's now the uber I/O architect at Intel, looking for ways to drive common technologies and practices across all wired and wireless I/O. Hey, it's the era of consolidation and cost savings, right? He says he is busy coming up to speed on everything from Ethernet to wireless USB. Wonder what sort of stew he will come up with from those ingredients?

Finally, my colleague Loring Wirbel is neck deep in news at Interop this week. Check out his story on optical cabling advances among others, and stay tuned for much more as Wirbelicious cooks up his own goulash this week over at EE Times.

1 comment:

Anonymous said...

First, there is nothing major going on with PCI Express technology. The 5 GT/s technology is in execution phase and given it is just a speed bump for a select set of usage models such as graphics or servers, the bulk of the I/O will stay with 2.5 GT/s. A set of extensions for PCI Express are being developed which are largely minor in nature and applicable to multiple market segments - ignore the Intel marketing hype as this isn't a new PCI Express just natural evolutionary functionality. So aside from a debate on third generation signaling, there isn't much going on and even that decision is focused on 2010 products so the hum-drum will continue.

Second, there isn't any "father" of PCI Express. No offense to Ajay but there were a significant number of people across the industry who created PCI Express. Ajay was simply the public voice so he got a great deal of attention. The fact is the bulk of the specifications were developed by others who often were not seen by the public.

Last keep in mind that the world is consolidating on fewer technologies. This is just a fact of life. People coming up to speed is simply a recognition that their world is changing and the value of the past is being re-evaluated. Techcnologies such as PCI Express will fade into the background and as we move towards system on a chip, its very long-term viability may be questioned but that in this industry, what is long-term isn't always a huge number of years. Most will say it is safe to project 2012 as solid for the technology but beyond that, the world gets hazy.

 
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