Friday, April 13, 2007

The road to 3-D chips

I learned a lot about the future of chip-to-chip interconnects from covering IBM's announcement yesterday that it is ready to build its first commercial chip using through-silicon vias, holes drilled directly through two die and filled with a metal link. My colleague Mark Lapedus had plowed significant ground on the topic in a story from the February ISSCC conference.


Perhaps the biggest news nugget I turned up pursuing this story yesterday is that the International Technology Roadmap for Semiconductors will sport a first-ever section on the roadmap for through-hole vias when it is published late this year. Thanks to Sitaram Arkalgud, who runs the interconnect group at Sematech, for giving me the run down.

There's plenty happening here, it is interesting technology and has huge implications for the future of chip and system design, a topic I will burrow into more in a story in Monday's EE Times.

So now that I have come up to speed a tad on the topic, look for me to weave this thread into the fabric of my interconnect coverage from time to time. I welcome your inputs on the topic by making a posting here or emailing me at rbmerrit@cmp.com

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