Wednesday, April 25, 2007

A new day for interconnect designers

You can learn a lot from reading the classified ads. I picked up one on the Signal Integrity email list recently that gave an interesting reality check about high-speed interconnect design in communications. An ad for a senior engineer for the Internet Systems division at Cisco Systems had the following eyebrow raiser:

“We are now engaged in the design of 6-8Gbps serial link interfaces. The Senior SI Engineer is expected to model legacy systems for 6-8Gbps operation, anddesign new systems to work at even higher line rates.” To handle that work the candidate needs to be able to “generate guidelines for new [chip] packages...and design experiments to” evaluate and characterize high-speed serdes. Besides having experience with a wide variety of high-speed design tools and test gear the person needs “a solid grasp” of a range of techniques including “microwave theory.”

The ad posting validated something I heard a while back from Todd Westerhoff, a senior SI engineer at Cisco who left last year to join the EDA world. Engineers in top tier comms companies are headed into a whole new era of design at 6G bits/s+. They have to become deeply astute about the details of things like chip packages as well as highly nuanced second-order signaling effects at the chip and board levels. That will require new tools, tests, gear and techniques unlike anything they have seen before.

Grab a coffee, sharpen your pencil and welcome to the new era in comms design.

BTW, I am still looking for any pointers about why Google is hiring signal integrity engineers for its Google Platforms group. I'd love to get my hot little hands on the specs of a Google server or systems interconnect!

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