Thursday, April 19, 2007

Modeling format percolates

Proponents of a new approach to high speed signal integrity modeling are turning up the heat on their efforts.

I reported from DesignCon in January on Cadence Design Systems' work on a new way to securely interrogate high speed chips. Now former Cadence signal integrity guru turned consultant Donald Telian suggests vendors may be getting ready to rally around the approach, much as they responded to his call 15 years ago to form the IBIS (I/O Buffer Information Specification) group.

"We may be on the verge of a new modeling format," writes Telian in a contributed article recently submitted for publication in EE Times.

The gist of Telian's point is that Cadence's algorithmic modeling approach "can compile Tx/Rx signal processing structures and algorithms in their native formats into executable models for an SI simulator…The beauty of the Cadence solution is that, in theory, the same models can be used by both the SI simulators and the test & measurement equipment."

The issue at hand is getting chip makers, EDA and test companies to understand and accept this new approach. No specific news on that front, but with Telian's enthusiasm on the topic, I suspect plenty of people are hearing about it.

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