Sunday, March 04, 2007

Intel drives multiple CPU buses


Two tiny details in an Intel server briefing last week gave a peak at some big moves in the X86 king's plans for attacking archrival Advanced Micro Devices.

What Intel suggested in its briefing is that its upcoming four-way Xeon code named Tigerton will sport four dedicated processor buses, each one linking a CPU to a chip set in a four-socket server. This could go quite a way to matching AMD's use of the cache coherent HyperTransport interconnect embedded on its Opteron CPUs to link four processors in a system.

Of course, Intel's Xeon will still lack an embedded memory controller so the Caneland system its Tigerton processors plug into will still have—at least theoretically--lower performance and higher cost than a four-way Opteron server.

It will be interesting to see whether Intel makes any technical tweaks in its processor bus as part of this move. I also wonder whether Intel will be more open about licensing the bus so other chip or system makers can design their own multiprocessing approaches. Perhaps this is a small step toward Intel's long-rumored, HyperTransport-like interconnect known as CSI.

Stay tuned for more details when Tigerton hits this fall.

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