Monday, February 19, 2007

Rapid I/O dives into backplane

Check out the story by Loring Wirbel in the print pages of this week’s EE Times if you want to get an update on Rapid I/O. The upshot is the group appears to be re-focusing on backplanes--as opposed to chip-to-chip interconnects--as a primary application.

That feels like a big shift to me, and I think I understand it. Back when it got started, RIO was essentially designed as the PowerPC native parallel processor bus, like HyperTranport on the AMD Opteron. But these days PCI Express is scooping up all the chip-to-chip traffic.

You might note the new dual-core Power PCs from P.A. Semi use Express, not RIO. It will be interesting to see what interface the PowerPC chips coming from AMCC this summer will use, given they were designed under the leadership of Dan Bouvier who drove much of the RIO and embedded PowerPC work while he was at Motorola Semi.

Will RIO find a home in backplanes? A cottage maybe. But just as Express is taking everybody’s attention in chip-to-chip links, so Ethernet is winning most design wins in backplanes, especially with all the interest in the IEEE backplane Ethernet standard.

My net on this is that RIO could go the way of the Advanced Switching Interconnect in a year or two.


Anonymous said...

Rick, I think your cottage metaphor is good. Rapidio appears to have found a place as the serial backplane upgrade for VME. And TI is using it on some of their DSPs (for now). So while I don't think it will die, it certainly will be a nichy standard. Maybe it should be called serial VME?

interconnect Guy said...

Hmm, I thought RapidIO was doing the backplane for sometime now, VME Chassis are shipping 3rd generation RapidIO backplanes, and ATCA backplanes and AMC cards are in all types of labs, check out Mercury's Ensamble one and two!
RapidIO is part of both these standards, and is a Switched Fabric vs. a Serial Interconnect like Express. Seems ASI was to be the solution to a weak Express in backplanes and beyond the PC.
So RapidIO in a backplane is hardly a 'big shift'. I see a very big list of available chips, boards, backplanes and systems that are currently in production from RapidIO Vendors. I don't see it going away! Since RapidIO can be a processor interconnect, do chip to chip with low overhead, and handle complex backplane data, as Loring points out; looks like it can do the job!

RapidIO Executive Director said...

Greetings, As RapidIO Executive Director a comment is due.
1. RapidIO is not going away!, in fact RapidIO is doing very well and positioned to support the needs of the embedded engineers for a bright and extended future.
The RapidIO Trade Assocation has a strong and focused membership and a large Eco-system of suppliers.
2. RapidIO preforms well as a Chip to Chip interconnect, with or without switches and as a full-featured switch fabric. That supports both the control and dataplane with carrier grade quality.
3. A number of interconnects are part of every system, Express, Ethernet and RapidIO all have strong value in systems, the question at hand, is which is best for the job being done? My view can be found in our webpages
Regards, Tom Cox, ED, RapidIO TA

Anonymous said...

RapidIO is not re-focusing in another direction, it seems to me that it is expanding from a foundation around chip-to-chip interconnect to also include backplane. This is a natural shift and not one that PCI Express (Serial PCI) can effectively do in many embedded applications.
I certainly agree that it will be interesting to see how new processors from AMCC enter the market and what happens when GigE can no longer meet the bandwidth requirements of the backplane.
Oh by the way, Advanced Switching went the way of the Dinosaur because Intel pulled a fast one and backed out as soon as they achieved their goal of getting an ecosystem following for Express around their PC/Server markets. Trust me, a lot of embedded semi vendors were left high a dry when their dreams of Intel driving the path into the embedded world vaporized.
From what I can see, there is more than one key processor vendor involved in RapidIO and many switch vendors shipping product. RapidIO exists because the Market is real not because Intel commanded it from on high.
PCIe rules in servers because you can live with one HOST/Root complex - Oh ya and Intel made it so. But in a multi-host, embedded environment you need something different. Desperate short term patches of serializing old technology won't cut it.. . . It seems to me that RapidIO is a compelling solution.

Anonymous said...

Dear "interconnect guy":

Since when is one DSP chip and errata-filled silicon from Freescale a "big list"?

I'm sure rapidio is a great technical solution but the best solution does not always win. Ethernet has proven time and again it is "good enough" for the job. Talk to the ATM, SONET, Infiniband, token ring, 100VG AnyLan, etc. guys if you need some case studies.

interconnect Guy said...

dear Anonyous
TI has several DSP's with RapidIO, and Freescale has a quad core DSP, I have a board with 4 Analog Devices DSP's, Check with your suppliers, many more DSP's and CPU's coming in roadmaps.
And since when is it about just DSP' and CPU's, how about switchs, FPGA's, and ASICs.
If you need a case study, the RapidIO whitepaper rings true with tests done in our lab.
Why pay for bandwidth and CPU overhead in ethernet to get QoS, when RapidIO delivers full bandwidth. Maybe the packet size your passing is very very big, then ATM, SONET and Infiniband are for you. But for the embedded systems we build for Telecom mixed control and data are the reality.

Palani said...

It is cost. Ethernet or a discrete general purpose PHY has become a commodity item. For Rapid I/O to get there, more participation from the entire food chain is needed.
With logical layer compatibility with PCI, PCI express is also getting there.

For datacom backplanes, most applications still use FPGAs on board. For cost sensitive applications using a low cost FPGA with a commodity SERDES might be more effective. All FPGA vendors offer free IP cores for the logical layers of pretty much any protocol.