Tuesday, January 30, 2007

PCI Express 3.0: 8, 10 or 12?

The ink on the 5GHz PCI Express spec is not even dry and the debate is already on about version 3.0.

Some say to heck with backward compatibility. It's time to make the break with the past and step boldly into a 10-12 Gbit/second interconnect.

Others say, no way. That would burn way too much power on high levels of equalization, 8 Gbit is enough. After all, even Express 2.0 will only effectively deliver 4 Gbits/second of data, so you will have an effective doubling. And Express traditionally stays a step behind the more aggressive comms serdes world of 3.125G, 6.5G and 10G so that PCs can benefit from more relaxed standards and costs. After all, those boards will all be built in low cost shops in Shenzhen.

I bet when the dust clears we will have an 8GHz Express 3.0. What do you think?

2 comments:

Anonymous said...

Pretty well a lock to be 10 T/s encoded- 8 Gbps of data

Anonymous said...

Isn't it ironic that the Intel PCI Express marketing juggernaut's main theme was PCI technology must move to serial technology and provide at least 2x performance upgrade roadmap in order to keep up with the rapid advances in processors and memory technology? Further, the juggernaut stated it was imperative that there be such rapid increases in performance to keep customers from turning to other technologies. Was the juggernaut wrong or did it stumble in its ability to deliver high performance processors and memory technology? Is it now worthwhile for the industry to turn to other technologies such as CSI or Hypertransport (at least Hypertransport is an open industry standard with many of the same companies who use PCI Express developing Hypertransport technology and products) to meet its high performance needs?

I'm sure the marketing teams are spinning their material quickly to justify the inability to deliver the promise of 2x performance improvements with every major release as we speak - guess a nearly 15 year track record might finally come to a close. They'll find areas to duck and cover behind their inability to execute a 2x performance boost. They'll claim interoperability is required with prior PCI Express versions but is it really? No matter the signaling rate, the mechanical connector will need to be reworked and while prior HBA may fit, it is still a new connector. No matter the signaling rate, any signaling increase reduces the effective distances supported and impacts topology and platform designs. No matter the signaling rate, power consumption will increase if distance is to be maintained. No matter the signaling rate, if it does not meet workload requirements or forces the industry to move to wider links in order to compensate, things will not look pretty - power, cost, routing complexity, and so on and so forth will all rise bringing significant credibility challenges to the ability of PCI Express to be viewed as a viable technology for any high-speed I/O or graphics.

The challenges for PCI Express 3.0 are about delivering performance while keeping power, cost, and adoption rates.in mind. Switching to a new more efficient encoding scheme is one option to reduce the signaling rate and save cost and power. The current 8b/10b encoding, while rather ubiquitous within the industry is still not the most bandwidth efficient technology. Other schemes have been proposed and implemented in other technologies so why not take that learning and apply it to PCI Express?

The question for the industry isn't the signaling rate. The question is whether PCI Express performance has hit a wall where it will no longer keep up with customer workloads. I'm sure Alienware and others will already be pushing PCI Express 2.0 chipsets to operate at 40-50% more than the stated signaling rate already delivering an 8 Gbps performance level. If you are correct and PCI Express 3.0 only delivers a 50% boost in performance, will these others deliver a 2X boost and capture market share from those who failed to deliver the necessary performance? Or will the industry simply view PCI Express 3.0 as the last of the PCI technologies and simply move to Hypertransport or perhaps CSI (will hell have frozen over should CSI actually be an open, industry standard)?

 
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