Wednesday, December 13, 2006

Trio of new 6Gbits/s+ links coming

I wrote on December 4 about how this month the PCI SIG may complete work on the PCI Express 2.0 spec for 5GHz chip-to-chip links. Tom Cox, executive director of the RapidIO Trade Association, was quick to point out his group is also working on a 2.0 spec defining 5 and 6GHz links.

The RIO 2.0 spec still has to pass a final ballot, but Cox and crew have been presenting the details to engineers on a road show that has traveled across the US, Japan, China and India. "I must say that 5 and 6.25 Gbps are not the urgent need of the industry today, but the technology is available and the definition is important by the standards body before a de-facto choice just happens," Cox said.

There's even more to come. Watch this space Monday for news about another 6Gbit/s+ interconnect about to hit the streets. This one relates to the Cisco/Cortina Interlaken work I blogged about on November 2.

Meanwhile, I'd love to hear what you think—oh, board designer in the field—about the requirements and challenges of pushing chip-to-chip links to 6GHz and beyond. Drop a post or an email to rbmerrit@cmp.com

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